Currently, the cost of nitride light emitting diodes is much higher than other illuminating devices, and sapphire substrates that are used for growth of nitride have shortcomings such as poor thermal conductivity which seriously affects their lifespan. Therefore, replacing the current sapphire substrate with a lower-cost and high thermal conductive substrate is the goal that major companies have been working on. Since silicon substrates have properties such as high thermal conductivity, high electrical conductivity, ability to be cut easily and low cost, the major companies have been competing to develop a light emitting diode based on a silicon substrate in recent years.
However, nitride semiconductor structures fabricated on silicon substrates have low production yields, so that the cost of the devices is difficult to decrease significantly. The main reason for affecting the yield of nitride semiconductor structures is coefficient of thermal expansion (CTE) mismatch and lattice mismatch between the nitride semiconductor layer and the silicon substrate, where the mismatch of lattice constant may cause the nitride semiconductor structures to crack easily and also cause the electric leakage, such that the illuminating efficiency may be affected.
When research and development (R&D) institutions and major companies manufacture the nitride semiconductor structure over a silicon substrate, a nucleation layer must be grown on the silicon substrate firstly, which is to prevent elements such as gallium (Ga) in the nitride semiconductor layer easily reacting with silicon to form compounds in the subsequent growth of the nitride semiconductor layer, such that the amorphous or non-monocrystalline may not be generated and the illuminating intensity of the light emitting diode may not be affected. FIG. 1 is a transmission electron microscope (TEM) image of a conventional nitride semiconductor structure. Referring to FIG. 1, the conventional nitride semiconductor structure 100 includes a silicon substrate 110, a nucleation layer 120, a buffer layer 130 and a nitride semiconductor layer 140. Since the lattice mismatch between the silicon substrate 110 and the nucleation layer 120 is considerably large (for instance, the lattice mismatch between the silicon substrate 110 and the nucleation layer 120 is greater than 17%, if the nucleation layer 120 including aluminum nitride (AlN) is exemplified), a large amount of defects may be generated on the interface between the silicon substrate 110 and the nucleation layer 120, as shown in FIG. 1. Although the nitride semiconductor layer 140 having a certain thickness is formed by the subsequent growth, it is difficult to prevent the generation of defects, so that the nitride semiconductor layer 140 has a relatively high defects density.
FIG. 2A is a transmission electron microscope (TEM) image of a conventional nitride semiconductor structure. Referring to FIG. 2A, the conventional nitride semiconductor structure 200 includes a silicon substrate 210, a nucleation layer 220, a buffer layer 230, a defect blocking layer 235 and a nitride semiconductor layer 240. In the conventional nitride semiconductor structure 200, the defect blocking layer 235 is formed on the buffer layer 230 to block the defects. In addition, the defect blocking layer 235 may reduce the lattice defects occurred in the nitride semiconductor layer 240 during the epitaxial growth process, and may release stress. However, due to most defects are formed at the interface between the silicon substrate 210 and the nucleation layer 220, the defect amount blocked by the defect blocking layer 235 is limited since the defect blocking layer 235 is formed on the buffer layer 230. In addition, the defect blocking layer 235 is usually an amorphous layer, and the subsequently formed nitride semiconductor layer 240 grows on the defect blocking layer 235 and is required to have a flat top surface. In other words, coalescence of the nitride semiconductor layer 240 is necessary. Nevertheless, the growth of the defect blocking layer 235 may cause stress, so that the nitride semiconductor structure 200 may easily crack while cooling. Therefore, the flat top surface of the nitride semiconductor layer 240 must be formed less than a certain thickness, so as to reduce the stress.
FIG. 2B is an enlarged view of the nitride semiconductor structure in FIG. 2A being enlarged 20 times by the optical microscopy (OM). Referring to FIG. 2B, there are a plurality of voids in the nitride semiconductor layer 240. This is because the nitride semiconductor layer 240 only grows on the defect blocking layer 235 to have the certain thickness for reducing the stress. However, the thickness of the nitride semiconductor layer 240 is insufficient, so that coalescence of the nitride semiconductor layer 240 is difficult to be achieved.